In DMA transfers, the required signals and addresses are given by the __________

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In DMA transfers, the required signals and addresses are given by the __________

1.Processor

2. Device drivers

3.DMA controllers

4. The program itself

Posted Date:-2021-03-15 06:07:33

More MCQS Questions and answers

  1. ______ interrupt method uses register whose bits are set separately by interrupt signal for each device
  2. A privilege exception is raised __________
  3. A single Interrupt line can be used to service n different devices.
  4.  After the completion of the DMA transfer, the processor is notified by __________
  5.  An interrupt that can be temporarily ignored is ___________
  6.  How can the processor ignore other interrupts when it is servicing one _________
  7.  If during the execution of an instruction an exception is raised then __________
  8.  In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
  9.  Interrupts initiated by an instruction is called as _______
  10.  The 8085 microprocessor responds to the presence of an interrupt __________
  11.  The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is ___________
  12.  The method of accessing the I/O devices by repeatedly checking the status flags is ___________
  13.  The return address from the interrupt-service routine is stored on the ___________
  14.  The starting address sent by the device in vectored interrupt is called as __________
  15.  To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
  16. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged.
  17. How is a privilege exception dealt with?
  18. In daisy chaining device 0 will pass the signal only if it has ___
  19. In DMA transfers, the required signals and addresses are given by the __________
  20. In trace mode of operation is ________
  21. In vectored interrupts, how does the device identify itself to the processor?
  22. Interrupts form an important part of _____ systems.
  23. In memory-mapped I/O ____________
  24. The added output of the bits of the interrupt register and the mask register is set as an input of ______________
  25. The advantage of I/O mapped devices to memory mapped is _________
  26. The code sent by the device in vectored interrupt is _____ long.
  27. The DMA differs from the interrupt mode by __________
  28. The DMA transfers are performed by a control circuit called as __________
  29. The instructions which can be run only supervisor mode are?
  30. The interrupt-request line is a part of the ___________
  31. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?
  32. The method which offers higher speeds of I/O transfers is ___________
  33. The process wherein the processor constantly checks the status flags is called as ___________
  34. The processor indicates to the devices that it is ready to receive interrupts ________
  35. The program used to find out errors is called __________
  36. The resistor which is attached to the service line is called _____
  37. The signal sent to the device from the processor to the device after receiving an interrupt is _______
  38. The system is notified of a read or write operation by ___________
  39. The time between the receiver of an interrupt and its service is ______
  40. The two facilities provided by the debugger is __________
  41. The usual BUS structure used to connect the I/O devices is ___________
  42. What are the different modes of operation of a computer?
  43. What is the operation in Breakpoint mode?
  44. When dealing with multiple devices interrupts, which mechanism is easy to implement?
  45. Which interrupt is unmaskable?
  46. Which table handle stores the addresses of the interrupt handling sub-routines?
  47. ___ is/are types of exceptions.
  48. ________ method is used to establish priority by serially connecting all devices that request an interrupt.
  49. ____________ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.
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